Designation: ASST. PROF.

Qualification: M.E, pursuing PhD

Email-id: [email protected]

Experience: 3.5 yrs

Industrial experience: 9 yrs



Title of Paper/Journal/ Conference Date
1.     A technical paper on “Verification of a RISC processor IP core using system Verilog”  was presented  in WiSPNET 2016 (IEEE). 2016
2.     A paper on “ An effective implementation of Rate ¾ Trellis Codec in DMR Systems” in KETCON 2016 2016
3.     A paper on “A Comparative Study of Multimodal face recognition based on Modular PCA and Modular SIFT” in KETCON 2016 2016